Specifically, but not exclusively, the present invention concerns a circuit of the above mentioned type and comprises a comparator having at least two inputs and an output. The comparator receives a first reference signal from a generator block and a second signal proportional to a supply voltage from a divider block to produce an initialization signal as an output. As known, a common problem with nearly all digital electronic devices is the correct initialization of the device upon starting.
Specifically, digital electronic devices are normally associated with a so-called power on circuit which controls turning on of electric power and performs a reinitialization, or reset, of the digital device. In technical jargon the practice of denominating starting circuits assigned to the above mentioned reinitialization `power on reset` is established.
The main function of the power on reset circuit is to generate a POR signal for a digital device. This signal is generated downstream of a comparison between the rising slope of a supply voltage of the digital device and a reference potential which is generally taken from a node inside the power on reset circuit. It is very important for correct operation of the circuit that the voltage value of this internal node reach the operating value in advance of the supply voltage. The comparison between the two voltage values is performed by a comparator which produces at output an INTPOR signal on which the POR signal depends directly.
In FIG. 1 is shown an example of a power on reset circuit provided in accordance with the prior art. The internal reference node is indicated by the block RIF which is directly connected to an input of the comparator, while the block Vdd|div indicates a division of the supply voltage supplied to a second input of the comparator. The output of the comparator is coupled to the supply voltage Vdd through a capacitor C and is also connected to an output buffer which produces the POR signal.
The Vdd|div block produces an output voltage having the same linear behavior as the supply voltage Vdd, but with a slope reduced by a factor m. The factor m is for all purposes a division ratio which must be ensured with accuracy and stability. The capacitor C has the function of favoring the coupling of the INTPOR signal with the supply voltage Vdd during the rising transient thereof. In rated operation the value of INTPOR remains fixed from the comparator output.
The output buffer has the purpose of decoupling the dynamics of the output signal POR which has a range equal to the power supply Vdd from that of the intermediate signal INTPOR which can have a smaller range. This allows increasing the response speed of the circuit and driving the POR line which has a high fan-out.
Although advantageous in some ways the power on reset circuit described above displays the serious shortcoming of excessive power consumption. Indeed, all the circuitry must necessarily remain on to be able to promptly regenerate the POR signal in case of a drop in supply voltage. This requires the presence of a rated current other than zero. Such rated behavior is undesirable for low consumption digital devices, such as, for example, those incorporated in cellular telephones.
Attention is drawn also to all the flash semiconductor memories powered, for example, with low voltage between 2.5 V and 3.6 V and for which is required a virtually null current (maximum 5 .mu.A) on stand-by.
The technical problem underlying the present invention is to conceive a power on reset circuit having structural and functional characteristics, such as to allow virtually null current consumption in stand-by, while maintaining the characteristics of promptness in generating the power on reset signal in case of a drop in the power supply. This would allow overcoming the limitations and shortcomings of the present solutions proposed by the prior art.